In the quest for improved performance, electronic circuits are becoming denser and devices smaller. For example, the most common gate dielectric in metal-oxide semiconductor field-effect transistors (MOSFETs) has been SiO2. However, as the thickness of SiO2 approaches 15 Å, substantial problems appear, including large leakage currents through the gate dielectric, concerns about the long-term dielectric reliability, and difficulty of manufacture and thickness control. A solution to the problem is to use thick films of materials, such as hafnium oxide (HfO2) and/or zirconium oxide (ZrO2) which have a dielectric constant larger than SiO2. Thus, the physical thickness of the gate dielectric can be large, while the electrical equivalent thickness relative to SiO2 films can be scaled. The electrical equivalent thickness (teq) of a high dielectric constant material, relative to SiO2, for example, may be calculated by the formula:teq=tphy(εSiO2/εhigh-k)where tphy is the actual thickness of the substitute metal oxide gate dielectric, such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, yttrium oxide, lanthanum aluminum oxide, and the like, and where εSiO2 and εhigh-k are the dielectric constants of SiO2 and the metal oxide gate dielectric film, respectively. Similar problems are encountered in scaling capacitors in memory devices. As the circuits become denser and the devices smaller, a material with a higher capacitance, such as HfO2, ZrO2, or Al2O3, is necessary to store adequate charge in the capacitor. High-k dielectrics, such as HfO2, ZrO2, or Al2O3, have dielectric constants more than double the dielectric constant of SiO2 (k=4) and are thus an attractive material for replacement of SiO2 in transistors and capacitors. The term “high-k” denotes a dielectric having a dielectric constant of greater than SiO2, preferably 7 or above.
Introduction of high-k dielectrics, such as HfO2, ZrO2, or Al2O3, in gate stacks have proven to reduce leakage current by several orders of magnitude. Such leakage reduction has enabled the fabrication of CMOS devices with low power consumption. Unfortunately, other problems have arisen from utilizing high-k dielectrics in CMOS devices including difficulty in passivating the underlying silicon, the introduction of unwanted charges in the gate stack which produce large flat band voltage shifts, large threshold voltage shifts, significant charge trapping, and low mobility devices.
Additionally, introduction of high-k dielectrics has necessitated deposition method development to ensure growth of high quality films. Previous work with high-k dielectric precursors have utilized conventional bubbler technology which involves a carrier gas bubbled through a neat (i.e., without solvent) precursor at an elevated temperature. The conventional bubbler technology relies on a consistent vapor pressure of the precursor to deliver a uniform precursor flux to the film and thus ensure a reproducible growth rate. However, control of growth rate necessary to achieve thin films (<100 Å) is difficult with conventional bubbler technology, due to fluctuations in precursor flux caused by variations in bubbler temperature, first run effects (bubbler held at elevated temperature in static conditions over time will have a higher volatilized precursor concentration, than a bubbler which is dynamically purged), and precursor volatility changes due to sintering of solids and/or precursor decomposition. Elevated temperatures and thermal cycling of a precursor in a conventional bubbler may contribute to premature degradation by ligand rearrangement, cluster formation, or oxidation of liquid and solid precursors over time. Additionally, precursor selection is critical to ensure adequate volatility, sufficient stability to prevent degradation during storage, transport, and vaporization and to ensure that the precursor has an optimal decomposition pathway to minimize impurities in the oxide film which would lead to degradation in electrical performance.
An additional problem with high-k dielectrics is that they tend to be oxygen deficient. To reduce leakage current associated with this oxygen deficiency, a post deposition anneal in oxygen at a high temperature is often conducted. This anneal in oxygen often grows an interfacial SiO2 layer at the interface between the high-k dielectric and the underlying silicon. The interfacial SiO2 layer reduces the effectiveness of the high-k dielectrics, since SiO2 has a lower dielectric constant and thus reduces the effective capacitance of the film. Additionally, an interfacial layer may grow between the high-k dielectric and a top polysilicon electrode.
An additional problem associated with post deposition annealing of the above-mentioned high-k dielectrics is that during post deposition annealing, crystallization and grain growth may occur. As a result, the surface of the annealed film may roughen. Surface roughness causes non-uniform electrical fields in the channel region adjacent the dielectric film. Such films are not suitable for the gate dielectrics of MOSFET devices.
An additional problem associated with high-k dielectrics is their sensitivity to reducing conditions, specifically to forming gas anneals. To restore the silicon properties of the MOSFET/CMOS, the manufacturing process typically includes a forming gas or hydrogen anneal step, in which defects in the silicon such as dangling bonds are eliminated by utilizing the reducing effect of hydrogen. However, subjection of a metal oxide to a reducing environment commonly results in diminished electronic properties due to reduction of the metal oxide. Commonly, a dramatic increase in leakage current is observed. Strategies such as recovery anneal in oxygen to reoxidize the metal oxide has the disadvantage of negating the effect of the forming gas anneal on the underlying silicon. Encapsulation techniques and barrier layers to slow the diffusion of hydrogen to the metal oxide require additional processing steps and are not completely effective.